Chapter 5
|
Processor Types And Instruction Sets
|
| 5.1 |
Introduction
|
61
|
| 5.2 |
Mathematical Power, Convenience And Cost
|
61
|
| 5.3 |
Instruction Set And Representation
|
62
|
| 5.4 |
Opcodes, Operands, And Results
|
63
|
| 5.5 |
Typical Instruction Format
|
63
|
| 5.6 |
Variable-Length Vs. Fixed-Length Instructions
|
63
|
5.7
|
General-Purpose
Registers
|
64
|
5.8
|
Floating Point
Registers And Register Identification
|
65
|
5.9
|
Programming With
Registers
|
65
|
5.10
|
Register Banks
|
66
|
5.11
|
Complex ANd Reduced
Instruction Sets
|
67
|
5.12
|
RISC Design And The
Execution Pipeline
|
68
|
5.13
|
Pipelines And
Instruction Stalls
|
69
|
5.14
|
Other Causes Of
Pipeline Stalls
|
71
|
5.15
|
Consequences For
Programmers
|
71
|
5.16
|
Programming, Stalls,
And No-Op Instructions
|
72
|
5.17
|
Forwarding
|
72
|
5.18
|
Types Of Operations
|
73
|
5.19
|
Program Counter,
Fetch-Execute, And Branching
|
73
|
5.20
|
Subroutine Calls,
Arguments, And Register Windows
|
75
|
5.21
|
An Example
Instruction Set
|
76
|
5.22
|
Minimalistic
Instruction Set
|
78
|
5.23
|
The Principle Of
Orthogonality
|
79
|
5.24
|
Condition Codes And
Conditional Branching
|
80
|
5.25
|
Summary
|
80
|