Chapter 6
|
Operand Addressing And Instruction Representation
|
| 6.1 |
Introduction
|
83
|
| 6.2 |
Zero, One, Two, Or Three Address Designs
|
83
|
| 6.3 |
Zero Operands Per Instruction
|
84
|
| 6.4 |
One Operand Per Instruction
|
85
|
| 6.5 |
Two Operands Per Instruction
|
85
|
| 6.6 |
Three Operands Per Instruction
|
86
|
6.7
|
Operand Sources And
Immediate Values
|
86
|
6.8
|
The Von Neumann
Bottlenec
|
87
|
6.9
|
Explicit And
Implicit Operand Encoding
|
88
|
6.10
|
Operands That
Combine Multiple Values
|
89
|
6.11
|
Tradeoffs In The
Choice Of Operands
|
90
|
6.12
|
Values In Memory And
Indirect Reference
|
91
|
6.13
|
Operand Addressing
Modes
|
92
|
6.14
|
Summary
|
93
|